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StackedArchitect/README.md

Typing SVG

As a final-year Electrical & Electronics Engineering student with a Minor in Computer Science, my primary passion lies in the world of computer architecture and RTL design. I am driven by the challenge of designing digital systems from the ground up—from writing Verilog for custom processors to verifying logic on FPGAs. While I enjoy building full-stack applications, my core focus is on the hardware that makes it all possible

  • 🔭 I’m currently exploring advanced RTL design for FPGAs and digital verification methodologies.
  • 🌱 My core interests are CPU Architecture, SoC Design, and High-Performance Computing.
  • ⚡ I believe in a meticulous approach to design, focusing on performance, efficiency, and robust verification.

🛠️ My Technical Toolkit

Hardware & Architecture
Verilog SystemVerilog Vivado Python C C++ RISC-V MIPS

Software & Full-Stack
TypeScript Java React Node.js

Databases, Tools & Platforms
MySQL Git


🏗️ Featured Hardware & Software Projects

A selection of projects showcasing my experience in RTL Design and Verification.

NOC MetaPyUVM - Network-on-Chip Testbench

A comprehensive Python-based testbench for Network-on-Chip (NOC) verification using PyUVM and Cocotb frameworks.

Python Verilog PyUVM Cocotb

View Repository →
Fault-Tolerant RISC-V Processor (Verilog)

A fault-tolerant, pipelined RISC-V processor featuring Triple Modular Redundancy (TMR) and SECDED memory protection. A deep dive into reliable computer architecture, designed for synthesis and verification.

Verilog Vivado Architecture Fault Tolerance

View Repository →
MIPS 32-Bit Pipelined CPU (Verilog)

A custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. This project demonstrates core CPU concepts and was verified using Python testbenches.

Verilog Python MIPS CPU Design

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Asynchronous and Synchronous FIFO

FIFO stands for "First-In, First-Out." It is a type of data structure or buffer in which the first data element added (the "first in") is the first one to be removed (the "first out"). This structure is commonly used in scenarios where order of operations is important.

Verilog Vivado FIFO

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Pinned Loading

  1. PMSM-FPGA-FOC PMSM-FPGA-FOC Public

    This project implements a Field-Oriented Control (FOC) system for motor control using FPGA. It includes modules for signal processing, control algorithms, and hardware interfacing, designed to opti…

    Verilog 4 1

  2. Fault-Tolerant-RISCV Fault-Tolerant-RISCV Public

    A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Des…

    Verilog 4

  3. MIPS32Bit-Pipelined-CPU MIPS32Bit-Pipelined-CPU Public

    This project is a custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. It demonstrates core CPU concepts and is ideal for learning…

    Verilog

  4. FIFO FIFO Public

    Synchronous and Asynchronous FIFOs

    Verilog

  5. FPGA_MNIST FPGA_MNIST Public

    This repo shows the implementation of MNIST dataset on an FPGA using MLP, 1D-CNN and 2D-CNN

    SystemVerilog

  6. FPGA_Hack FPGA_Hack Public

    Implementation of a Wavelet + BNN for Real-Time ECG Arrhythmia Detection on FPGA

    Python